In integrated circuit (IC) testing, the test technique of internal embedded scan design has become a cost effective solution to test the operation of ICs. Scan design is accomplished by altering the structure of standard flip-flops and latches (storage elements) within the IC into scan flip-flops and latches by providing a second alternate scan input for scan data parallel to the functional data input. The alternate input for scan data is generally implemented by placing a multiplexor in front of the standard input which selects either scan data or functional data. These “scannable” elements are then connected together in a serial shift register fashion by connecting the output of one element to the scan input of a next element via a “scan chain”. The scan chain can load and unload internal IC state information by allowing scan data to be transferred from one element to another on each active clock edge when a scan enable signal is asserted.
The static timing analysis (STA) closure frequency in automatic test pattern generation (ATPG) shift mode of the scannable storage circuits are quite high, but production test description languages (TDLs) are run at lower frequencies due to high IR drop and reliability issues caused by the complete design logic toggling in the ATPG shift mode. Combinatorial logic contributes to more than 40% of power consumption in scan mode. It is not required for the logic to toggle during ATPG shift. If the toggle on functional combinational logic can be stopped, the ATPG shift frequency can be increased significantly resulting in lesser test-time and hence lesser tester cost. The power consumption of the design depends upon the choice of a “pull-down” Q gating or a “pull-up” Q gating flop for a particular path. Post silicon test programs' development makes it difficult to decide on a type of circuit that ensures minimum test power for all possible TDL combinations, especially in case of partial usage of “gated Q” flops.
In functional mode of operation, the SD (scan input) pins of flops are connected to SQ (scan data out) pins of the previous flop. Whenever there is a signal activity on the D (functional data) pin of a flop, the signal travels to the SD pins of the subsequent flops, thereby causing unnecessary power loss. Considerable amount of power is burnt unnecessarily on test circuits in functional operations. When device is operated in overdrive modes (high frequency modes), the power loss becomes significant causing faster battery discharge.